Integrated circuits communicate with each other using electrical signals, often carried over a bus. A bus may include one or more interconnects, such as for example traces on a printed circuit board, wires, or cables and connectors. A bus may also be one or more traces or interconnects within an integrated circuit. A bus forms one or more signal paths that carry signals from an output driver to a receiver device. Both the sending and receiving devices may be integrated circuits. A bus may also be used to carry a signal between sending and receiver devices located on the same integrated circuit. As integrated circuits have evolved, many different signaling type standards have been defined that specify the characteristics of the electrical signals. The signaling type typically defines such characteristics as the reference voltage and duty cycle for the electrical signals. Examples of signaling types are stub-series terminated logic (SSTL), Rambus signaling level (RSL), HSTL, LVDS and DRSL (differential Rambus signaling level).
Buses are commonly employed for transmitting data, commands, clock signals or other information between computer devices. To properly receive data transmitted over a bus, the receiver typically has the capability of synchronizing itself with a clock signal that is transmitted in parallel with the data. Thus, an output driver may transmit both a data signal and a clock or synchronization signal to allow the receiver to properly receive and decode the transmitted data.
The speed and integrity of signals transmitted over a bus are often of critical importance. An output driver sends a data stream that has a specific duty cycle which should correspond to the synchronization signal of the output driver. A receiver reads and processes the data stream using a specific receiving duty cycle.
To maximize the speed and integrity of the transmission of the data stream, ideally the receiver's duty cycle matches the duty cycle of the received data signal. By having the duty cycles match, the receiver is configured to read the data stream with the eye of the data centered within a read cycle of the receiver and having a sufficient margin for the data to be read fully within the read cycle. The eye of the data represents a mid-point of the data within the data stream to be read during a single read cycle of the receiver.
There are a variety of challenges associated with matching the duty cycle of the received data signal with the receiver's duty cycle. The receiver may receive data streams from multiple devices, each having its own output driver. Each device's output driver may have a different duty cycle. Although output drivers generate signals typically having about a 50% duty cycle, some output drivers generate signals having duty cycle between 45% and 55%, or even between 40% and 60%, where the duty cycle of a signal is defined as the amount of time that a first bit (or symbol) of a signal is asserted on a signal line divided by the total amount of time that the first and a next bit of the signal are asserted on the signal line. If the signal is periodic, such that the first, third, fifth, etc. bits have a first of two signal levels and the other bits, i.e., the second, fourth, sixth, etc. bits have the second of the two signal levels, then the duty cycle of the signal is the percentage of time that the signal is above a common mode voltage. In addition, there are many different factors that can affect the electric signals sent between devices. For example, the packaging methodology for an integrated circuit can affect the electric signals that are sent from the integrated circuit. Additionally, the duty cycle needed to synchronize the receiver with the data signal duty cycle may vary based on such factors as the physical distance the signal travels, the operating temperature of the receiver device, and the like.
Thus, the actual duty cycle of the data signal when it arrives at the receiver may vary from the target duty cycle of the output driver driving the data signal. When the duty cycle of the data signal and the duty cycle of the receiver are not matched, the data transmission is not optimal. As a result, errors may occur during data reception, causing a portion of the information within the data signal stream to be lost at the receiver. As a result of such duty cycle mismatching, the rate of data transmission may need to be slowed to ensure acceptable data transmission reliability, or information may need to be transmitted multiple times to ensure acceptable reliability.
It would be beneficial to be able to tune the duty cycle of a receiver in real time to accommodate variations in the duty cycles of the data received by the receiver. It would be beneficial to adjust a receiver's clock duty cycle to match the duty cycle of a received data signal. Specifically, it would be beneficial to adjust a receiver's clock duty cycle to a duty cycle that is not always 50% in order to match the receiving clock duty cycle to the duty cycle of an incoming data signal. Additionally, it would be beneficial to have circuits that are able to communicate utilizing different signaling types.